FPGA类型

xilinx K7

仿真记录

模块例化

    IDELAYE2 #(.CINVCTRL_SEL("FALSE"),          // Enable dynamic clock inversion (FALSE, TRUE).DELAY_SRC("IDATAIN"),           // Delay input (IDATAIN, DATAIN).HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE").IDELAY_TYPE("FIXED"),           // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE.IDELAY_VALUE(31),                // Input delay tap setting (0-31).PIPE_SEL("FALSE"),              // Select pipelined mode, FALSE, TRUE.REFCLK_FREQUENCY(200.0),        // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0)..SIGNAL_PATTERN("DATA")          // DATA, CLOCK input signal)IDELAYE2_inst (.CNTVALUEOUT(), // 5-bit output: Counter value output.DATAOUT(data_out),         // 1-bit output: Delayed data output.C(1'b1),                     // 1-bit input: Clock input.CE(1'b1),                   // 1-bit input: Active high enable increment/decrement input.CINVCTRL(1'b0),       // 1-bit input: Dynamic clock inversion input.CNTVALUEIN(0),   // 5-bit input: Counter value input.DATAIN(1'b0),           // 1-bit input: Internal delay data input.IDATAIN(data_in),         // 1-bit input: Data input from the I/O.INC(1),                 // 1-bit input: Increment / Decrement tap delay input.LD(1),                   // 1-bit input: Load IDELAY_VALUE input.LDPIPEEN(1'b0),       // 1-bit input: Enable PIPELINE register to load data input.REGRST(1'b0)            // 1-bit input: Active-high reset tap-delay input);

modelsim仿真波形

 

 

仿真结果

rgmii_rx_ctl_delay和rgmii_rxd_delay信号是RGMII接口输入信号rgmii_rx_ctl和rgmii_rxd经过IDELAYE2延迟的信号，RGMII接口输出信号rgmii_tx_ctl和rgmii_txd是rgmii_tx_ctl_nodelay和rgmii_txd_nodelay信号经过ODELAYE2延迟的信号，IDELAYE2和ODELAYE2的输入输出本身有600ps的延迟，另外可以通过设置IDELAYE2和ODELAYE2里的IDELAY_VALUE和ODELAY_VALUE参数来增加延迟，这两个参数取值在0到31之间，表示增加几个标准延迟tap，tap与参考时钟频率f之间的关系是：tap=1/(64*f)，单位为ps，参考时钟频率f一般为200MHz或300MHz，如果f为200M，则tap=78ps，如果f为300M，则tap=52ps。以200M为例，当IDELAY_VALUE/ODELAY_VALUE参数值设为0，则IDELAYE2/ODELAYE2的延迟为600ps，当IDELAY_VALUE/ODELAY_VALUE参数值设为31，则IDELAYE2/ODELAYE2的延迟为（600+31*78）ps。在本仿真中，IDELAY_VALUE设的是8，ODELAY_VALUE设的是24，因此IDELAYE2的延迟为（600+8*78）=1224ps，ODELAYE2的延迟为（600+24*78）=2472ps。这两个参数值在正式工程中可根据实际情况调整。

 

仿真文件

//
// Design Name: 
// Module Name: example
// Project Name: 
// Target Devices: xc7k325tffg900-2
// Tool Versions: Vivado 2016.4 
//
`timescale 1ns/1psmodule tb_idelay();//**************************** Wire &  reg Declarations ******************localparam  IDELAY_EN = "YES" ;reg  lvds_clk_p ;wire lvds_clk_n ;wire lvds_clk_ibuf ;wire lvds_clk_dly ;reg  clk_200m ;wire [4:0] delay_tapout ;reg  [4:0] delay_tapin ;reg  rst ;
//******************************** main code *****************************initial begin lvds_clk_p = 1'b0 ;forever #4000  lvds_clk_p =  !lvds_clk_p ;end assign lvds_clk_n = !lvds_clk_p ;    initial begin clk_200m = 1'b0 ;forever #2500 clk_200m =  !clk_200m ;    end initial begin rst = 1'b1 ;delay_tapin = 5'd10 ;#1000000 ; rst = 1'b0 ;delay_tapin = 5'd1 ;#1000000 ;delay_tapin = 5'd8 ;#1000000 ;delay_tapin = 5'd15 ;#1000000 ;delay_tapin = 5'd23 ;#1000000 ;delay_tapin = 5'd31 ;#1000000 ;$stop ;end IBUFDS #(.DIFF_TERM("FALSE"),       // Differential Termination.IBUF_LOW_PWR("TRUE"),     // Low power="TRUE", Highest performance="FALSE" .IOSTANDARD("DEFAULT")     // Specify the input I/O standard) IBUFDS_inst (.O(lvds_clk_ibuf),  // Buffer output.I(lvds_clk_p),  // Diff_p buffer input (connect directly to top-level port).IB(lvds_clk_n) // Diff_n buffer input (connect directly to top-level port));generate if(IDELAY_EN == "YES" )begin : idelay_enable IDELAYE2 #(.CINVCTRL_SEL         ( "FALSE"      ),// Enable dynamic clock inversion (FALSE, TRUE).DELAY_SRC            ( "IDATAIN"    ),// Delay input (IDATAIN, DATAIN).HIGH_PERFORMANCE_MODE( "FALSE"      ),// Reduced jitter ("TRUE"), Reduced power ("FALSE").IDELAY_TYPE          ( "VAR_LOAD"   ),// FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE.IDELAY_VALUE         ( 0            ),// Input delay tap setting (0-31).PIPE_SEL             ( "FALSE"      ),// Select pipelined mode, FALSE, TRUE.REFCLK_FREQUENCY     ( 200.0        ),// IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0)..SIGNAL_PATTERN       ( "CLOCK"      ) // DATA, CLOCK input signal)IDELAYE2_inst (.CNTVALUEOUT          ( delay_tapout ), // 5-bit output: Counter value output.DATAOUT              ( lvds_clk_dly ), // 1-bit output: Delayed data output.C                    ( clk_200m     ), // 1-bit input: Clock input.CE                   ( 1'b0         ), // 1-bit input: Active high enable increment/decrement input.CINVCTRL             ( 1'b0         ), // 1-bit input: Dynamic clock inversion input.CNTVALUEIN           ( delay_tapin  ), // 5-bit input: Counter value input.DATAIN               ( 1'b0         ), // 1-bit input: Internal delay data input.IDATAIN              ( lvds_clk_ibuf), // 1-bit input: Data input from the I/O.INC                  ( 1'b0         ), // 1-bit input: Increment / Decrement tap delay input.LD                   ( 1'b1         ), // 1-bit input: Load IDELAY_VALUE input.LDPIPEEN             ( 1'b0         ), // 1-bit input: Enable PIPELINE register to load data input.REGRST               ( rst          )  // 1-bit input: Active-high reset tap-delay input);//(* IODELAY_GROUP = <iodelay_group_name> *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRLend else begin : idelay_disable assign lvds_clk_dly = lvds_clk_ibuf ;end 
endgenerateendmodule