目录
0 前言
1 仿真目标
2 IDS-VDS
3 IDS-VGS
4 VTH
5 IDS-VGS(log)
6 Body bias(Ids-Vbs)
7 Body bias(Vth-Vbs)
8 Ids-Temperature
0 前言
记录一下来到skd上的强度比较大的一门课,数字集成电路2的lab设计还是蛮好的,该帖非详细教程只是单纯的写一些思虑并用作笔记,新手小白欢迎交流,有错勿喷!
1 仿真目标
主要仿真45nm MOS管的静态参数
2 IDS-VDS
2.1 simulation code
* 45nm NMOS Simulation
.options brief post probe.temp 25
.INCLUDE 'NMOS_VTL.inc'
.param Vdd=1.1vVgs nG 0 DC 1V
Vds nD 0 DC 1VM0 nD nG 0 0 NMOS_VTL L=50e-9 W=90e-9.dc Vds 0 1.1 0.01 Vgs 0.1 0.9 0.2.probe I(M0)
.print I(M0).end
2.2 simulation wave
3 IDS-VGS
3.1 simulation code
* 45nm NMOS Simulation
.options brief post probe.temp 25
.INCLUDE 'NMOS_VTL.inc'
.param Vdd=1.1vVgs nG 0 DC 1V
Vds nD 0 DC VddM0 nD nG 0 0 NMOS_VTL L=50e-9 W=90e-9.dc Vgs 0 Vdd 0.01.probe I(M0)
.print I(M0).end
3.2 simulation wave
4 VTH
4.1 simulation code
* 45nm NMOS Simulation
.options brief post probe.temp 25
.INCLUDE 'NMOS_VTL.inc'
.param Vdd=1.1vVgs nG 0 DC 1V
Vds nD 0 DC VddM0 nD nG 0 0 NMOS_VTL L=50e-9 W=90e-9.dc Vgs 0 Vdd 0.01.probe I(M0) vth(M0)
.print I(M0) vth(M0).end
4.2 simulation wave
5 IDS-VGS(log)
5.1 simulation code
* 45nm NMOS Simulation
.options brief post probe.temp 25
.INCLUDE 'NMOS_VTL.inc'
.param Vdd=1.1vVgs nG 0 DC 1V
Vds nD 0 DC 0.1M0 nD nG 0 0 NMOS_VTL L=50e-9 W=90e-9.dc Vgs -Vdd Vdd 0.01 Vds 0.1 1.1 1.probe I(M0)
.print I(M0).end
5.2 simulation wave
6 Body bias(Ids-Vbs)
6.1 simulation code
* 45nm NMOS Simulation
.options brief post probe.temp 25
.INCLUDE 'NMOS_VTL.inc'
.param Vdd=1.1vVgs nG 0 DC 1V
Vds nD 0 DC Vdd
Vbulk nB 0 DC 1VM0 nD nG 0 nB NMOS_VTL L=50e-9 W=90e-9.dc Vgs 0 Vdd 0.01 Vbulk -1.1 0 0.1 .probe I(M0)
.print I(M0).end
6.2 simulation wave
7 Body bias(Vth-Vbs)
7.1 simulation code
* 45nm NMOS Simulation
.options brief post probe.temp 25
.INCLUDE 'NMOS_VTL.inc'
.param Vdd=1.1vVgs nG 0 DC 1V
Vds nD 0 DC Vdd
Vbulk nB 0 DC 1VM0 nD nG 0 nB NMOS_VTL L=50e-9 W=90e-9.dc Vgs 0 Vdd 0.01 Vbulk -1.1 0 0.1 .probe I(M0) vth(M0)
.print I(M0) vth(M0).end
7.2 simulation wave
8 Ids-Temperature
8.1 simulation code
* 45nm NMOS Simulation
.options brief post probe.INCLUDE 'NMOS_VTL.inc'
.param Vdd=1.1vVgs nG 0 DC 0.5
Vds nD 0 DC VddM0 nD nG 0 0 NMOS_VTL L=50e-9 W=90e-9.dc TEMP 0 100 1 Vgs 0.1 0.5 0.4.probe I(M0)
.print I(M0).end