GIC400 Register

gic寄存器

gic寄存器，分为两部分，一部分是distributor的寄存器，另一部分是cpu interface的寄存器。
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两部分的寄存器，均是通过memory-mapped的方式来访问。

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Distribution

Distributor Control Register GICD_CTLR enable or disable distribution，global interrupt enable

在disable 期间，register工作正常，GICV2可以通过操作寄存器配置int的pending或active状态
Interrupt Controller Type Register, GICD_TYPER
• whether the GIC implements the Security Extensions
• the maximum number of interrupt IDs that the GIC supports
• the number of CPU interfaces implemented
• if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs).

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Distributor Implementer Identification Register, GICD_IIDR

Provides information about the implementer and revision of the Distributor.
Interrupt Group Registers, GICD_IGROUPRn

Typically, the reset value of all GICD_IGROUPR registers is zero, so that all interrupts are Group 0 unless reprogrammed as Group 1 by Secure accesses to the appropriate GICD_IGROUPR registers.
Interrupt Set-Enable Registers, GICD_ISENABLERn

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Disabling an interrupt only disables the forwarding of the interrupt from the Distributor to any CPU interface. It does not prevent the interrupt from changing state, for example becoming pending, or active and pending if it is already active.

Interrupt Clear-Enable Registers, GICD_ICENABLERn

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Writing a 1 to an GICD_ICENABLERn bit only disables the forwarding of the corresponding interrupt from the Distributor to any CPU interface. It does not prevent the interrupt from changing state, for example becoming pending, or active and pending if it is already active.

Interrupt Set-Pending Registers, GICD_ISPENDRn
Interrupt Clear-Pending Registers, GICD_ICPENDRn

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Interrupt Set-Active Registers, GICD_ISACTIVERn

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Interrupt Clear-Active Registers**, GICD_ICACTIVERn**

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Interrupt Priority Registers, GICD_IPRIORITYRn
- These registers are byte-accessible
- The GICD_IPRIORITYRs provide an 8-bit priority field for each interrupt supported by the
  GIC. This field stores the priority of the corresponding interrupt. 256
- A GIC might implement fewer than eight priority bits, but must implement at least bits [7:4]
  of each field.
- The number of implemented GICD_IPRIORITYRs is (8*(GICD_TYPER.ITLinesNumber+1)).
- The lower the value, the greater the priority of the corresponding interrupt.

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Interrupt Processor Targets Registers, GICD_ITARGETSRn
- The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
- These registers are byte-accessible.
- Has no effect on any active interrupt. This means that removing a CPU interface from a targets list does not cancel an active state for that interrupt on that CPU interface.Has an effect on any pending interrupts.
- The registers that contain the SGI and PPI interrupts are read-only and the value is the CPU number of the current access
- GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register.
Interrupt Configuration Registers, GICD_ICFGRn
- The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC.
- Before changing the value of a programmable Int_config field, software must disable the
  corresponding interrupt,
- The number of implemented GICD_ICFGRs is (2*(GICD_TYPER.ITLinesNumber+1)).
- SGI is level_sensitive

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Private Peripheral Interrupt Status Register, GICD_PPISR
- Enables a processor to access the status of the PPI inputs on the Distributor.
- A processor can only read the status of its own PPI and cannot read the status of PPIs for other processors

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Shared Peripheral Interrupt Status Registers, GICD_SPISRn

Enables a processor to access the status of the IRQS inputs on the Distributor.

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Software Generated Interrupt Register, GICD_SGIR

Controls the generation of SGIs.

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...

SGI Clear-Pending Registers, GICD_CPENDSGIRn

The GICD_CPENDSGIRs provide a clear-pending bit for each supported SGI and source processor combination

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SGI Set-Pending Registers, GICD_SPENDSGIRn

The GICD_SPENDSGIRn registers provide a set-pending bit for each supported SGI and source processor combination.

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