(1)FIFO(First In First Out,即先进先出),是一种数据缓冲器,用来实现数据先入先出的读写方式。
(2)FIFO存储器主要是作为缓存,应用在同步时钟系统和异步时钟系统中,在很多的设计中都会被使用,比如:多比特数据做跨时钟域处理、前后带宽不同步等都用到了FIFO。
(3)FIFO根据读写时钟是否相同,可以分为SCFIFO(同步FIFO)和DCFIFO(异步FIFO)。
(4)scfifo配置过程:
(5)scfifo的调用:
module scfifo
(input clk ,input reset_n ,input [7:0]data_in ,input wr_en ,input rd_en ,output [7:0]data_out ,output full ,output empty ,output [7:0]data_count );scfifo_8x256 scfifo_8x256_inst (.clk (clk ), // input wire clk.srst (~reset_n ), // input wire srst.din (data_in ), // input wire [7 : 0] din.wr_en (wr_en ), // input wire wr_en.rd_en (rd_en ), // input wire rd_en.dout (data_out ), // output wire [7 : 0] dout.full (full ), // output wire full.empty (empty ), // output wire empty.data_count (data_count) // output wire [7 : 0] data_count
); endmodule
(6)仿真文件代码:
`timescale 1ns / 1psmodule scfifo_tb;reg clk ;
reg reset_n ;
reg [7:0] data_in ;
reg wr_en ;
reg rd_en ;reg [1:0] cnt ;wire [7:0] data_out ;
wire full ;
wire empty ;
wire [7:0] data_count ;scfifo scfifo_inst
(.clk (clk ) ,.reset_n (reset_n ) ,.data_in (data_in ) ,.wr_en (wr_en ) ,.rd_en (rd_en ) ,.data_out (data_out ) ,.full (full ) ,.empty (empty ) ,.data_count (data_count) );initial clk = 1'd1;always #10 clk = ~clk;initial begin reset_n <= 1'd0;#21;reset_n <= 1'd1;#100_000;$stop;endalways@(posedge clk or negedge reset_n)if(!reset_n)cnt <= 2'd0;else if(cnt == 2'd3)cnt <= 2'd0;else cnt <= cnt + 2'd1;always@(posedge clk or negedge reset_n)if(!reset_n)wr_en <= 1'd0;else if(cnt == 2'd3 && rd_en == 1'd0)wr_en <= 1'd1;elsewr_en <= 1'd0;always@(posedge clk or negedge reset_n)if(!reset_n)data_in <= 8'd0;else if(data_in == 8'd255 && wr_en)data_in <= 8'd0;else if(wr_en && (!full))data_in <= data_in + 8'd1;else data_in <= data_in;always@(posedge clk or negedge reset_n)if(!reset_n)rd_en <= 1'd0;else if(full && wr_en == 1'd0)rd_en <= 1'd1;else if(empty)rd_en <= 1'd0;else rd_en <= rd_en;endmodule
(7)仿真波形: