时间：2024.12.23
Dff8ar
代码
注意敏感信号的写法
module top_module (input clk,input areset, // active high asynchronous resetinput [7:0] d,output [7:0] q
);always@(posedge clk or posedge areset)beginif(areset) q<=8'b0;else q<=d;end
endmodule
module top_module (input clk,input areset, // active high asynchronous resetinput [7:0] d,output [7:0] q
);always@(posedge clk or posedge areset)beginq<=areset==1?8'd0:d;end
endmodule
运行结果
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Dff16e
代码
注：byteena[1]控制输入数据d的高八位，byteena[0]控制输入数据d的低八位，未被控制部分保持输出。
module top_module (input clk,input resetn,input [1:0] byteena,input [15:0] d,output [15:0] q
);always@(posedge clk)beginif(resetn==0)beginq<=16'd0;end else begincase(byteena)2'b10:q<={d[15:8],q[7:0]};2'b01:q<={q[15:8],d[7:0]};2'b11:q<={d[15:8],d[7:0]};default:q<=q;endcaseendend
endmodule
运行结果
Exams/m2014 q4a
代码
module top_module (input d, input ena,output q);always@(*)if(ena) q<=d;else q<=q;endmodule
module top_module (input d, input ena,output q);always@(*)beginq<=ena==1?d:q;end
endmodule
注：1)锁存器是电平敏感，不是边沿敏感；2）锁存器虽然是电平敏感，但是是时序电路，用非阻塞赋值<=。
运行结果
Exams/m2014 q4b
代码
module top_module (input clk,input d, input ar, // asynchronous resetoutput q);always@(posedge clk or posedge ar)beginq<=ar==1?1'b0:d;end
endmodule
module top_module (input clk,input d, input ar, // asynchronous resetoutput q);always@(posedge clk or posedge ar)beginif(ar) q<=1'b0;else q<=d;end
endmodule运行结果
Exams/m2014 q4c
代码
module top_module (input clk,input d, input r, // synchronous resetoutput q);always@(posedge clk)beginif(r) q<=1'b0;else q<=d;end
endmodule
module top_module (input clk,input d, input r, // synchronous resetoutput q);always@(posedge clk)beginq<=r==1?1'b0:d;end
endmodule
运行结果
Exams/m2014 q4d
代码
module top_module (input clk,input in, output out);wire d;assign d=in^out;always@(posedge clk)beginout<=d; end// assign d=in^out;
endmodule
注：组合逻辑的语句放在时序逻辑的前/后均可以
module top_module (input clk,input in, output out);always@(posedge clk)beginout<=in^out;end
endmodule
运行结果
Mt2015 muxdff
代码
module top_module (input clk,input L,input r_in,input q_in,output reg Q);
reg D;assign D=L?r_in:q_in;always@(posedge clk)Q<=D;
endmodule
module top_module (input clk,input L,input r_in,input q_in,output reg Q);always@(posedge clk)beginQ<=L==1?r_in:q_in;end
endmodule
运行结果
Exams/2014 q4a
代码
module top_module (input clk,input w, R, E, L,output Q
);
reg d;assign d=L?R:(E?w:Q);always@(posedge clk)beginQ<=d;end
endmodule
module top_module (input clk,input w, R, E, L,output Q
);always@(posedge clk)beginQ<=L==1?R:(E==1?w:Q);end
endmodule
运行结果
Exams/ece241 2014 q4
代码
module top_module (input clk,input x,output z
); wire q1,q2,q3;always@(posedge clk)beginq1<=(x^q1);q2<=(x&~q2);q3<=(x|~q3);endassign z=~(q1|q2|q3);
endmodule
运行结果
Exams/ece241 2013 q7
代码
module top_module (input clk,input j,input k,output Q); always@(posedge clk)beginif(~j&k) Q<=1'b0;else if(j&~k) Q<=1'b1;else if(j&k) Q<=~Q;else Q<=Q;end
endmodule
运行结果
