1位的与非门
代码：
`timescale 1ns/10ps
module nand_gate(
A,
B,
Y);input A;
input B;
output Y;assign Y=~(A&B);endmodule//testbenchmodule nand_gate_tb;
reg A;
reg B;
wire Y;nand_gate nand_gate(.A(A),.B(B),.Y(Y));initial begin A<=0;B<=0;#10 A<=0;B<=1;#10 A<=1;B<=0;#10 A<=1;B<=1;#10 A<=0;B<=0;#10 $stop;
endendmodule实验波形
4位的与非门
代码：
`timescale 1ns/10ps
module nand_gate_4bits(
A,
B,
Y);input[3:0] A;
input[3:0] B;
output[3:0] Y;assign Y=~(A&B);endmodule//testbenchmodule nand_gate_4bits_tb;
reg[3:0] A;
reg[3:0] B;
wire[3:0] Y;nand_gate_4bits nand_gate_4bits(.A(A),.B(B),.Y(Y));initial begin A<=4'b0000;B<=4'b0000;#10 A<=4'b0000;B<=4'b0001;#10 A<=4'b0001;B<=4'b0010;#10 A<=4'b1011;B<=4'b0011;#10 A<=4'b1001;B<=4'b1011;#10 A<=4'b1101;B<=4'b1001;#10 A<=4'b0101;B<=4'b1010;#10 A<=4'b0111;B<=4'b0011;#10 $stop;
endendmodule实验波形
