一、查看原理图，需要将GPIO_0、GPIO_1、GPIO_2、GPIO_3配置成SPI接口
二、查看安SDM450平台的数据手册，文档号：80-PC173-1,查看相关的手册可知，GPIO_0、GPIO_1、GPIO_2、GPIO_3可以复用成SPI1，
三、查看高通的文档号：80-NU767-1，SDM450使用的是MSM8953，设备树相关的地址要按照如下的方式配置和使用
四、DTS的设置，相关的地址配置是根据三的地址设置的：
diff --git a/arch/arm64/boot/dts/qcom/msm8953-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/msm8953-pinctrl.dtsi
index 070c558..aa6b0e2 100644
--- a/arch/arm64/boot/dts/qcom/msm8953-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8953-pinctrl.dtsi
@@ -1227,6 +1227,68 @@};};+ spi1 {
+ spi1_default: spi1_default {
+ /* active state */
+ mux {
+ /* MOSI, MISO, CLK */
+ pins = "gpio0", "gpio1", "gpio3";
+ function = "blsp_spi1";
+ };
+
+ config {
+ pins = "gpio0", "gpio1", "gpio3";
+ drive-strength = <12>; /* 12 MA */
+ bias-disable = <0>; /* No PULL */
+ };
+ };
+
+ spi1_sleep: spi1_sleep {
+ /* suspended state */
+ mux {
+ /* MOSI, MISO, CLK */
+ pins = "gpio0", "gpio1", "gpio3";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio0", "gpio1", "gpio3";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-down; /* PULL Down */
+ };
+ };
+
+ spi1_cs0_active: cs0_active {
+ /* CS */
+ mux {
+ pins = "gpio2";
+ function = "blsp_spi1";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>;
+ bias-disable = <0>;
+ };
+ };
+
+ spi1_cs0_sleep: cs0_sleep {
+ /* CS */
+ mux {
+ pins = "gpio2";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>;
+ bias-disable = <0>;
+ };
+ };
+ };
+
+
+spi3 {spi3_default: spi3_default {/* active state */
diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi
index ab85d27..535ec9e 100644
--- a/arch/arm64/boot/dts/qcom/msm8953.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi
@@ -194,6 +194,7 @@i2c2 = &i2c_2;i2c3 = &i2c_3;i2c5 = &i2c_5;
+ spi1 = &spi_1;spi3 = &spi_3;};@@ -644,6 +645,34 @@qcom,summing-threshold = <10>;};+ spi_1: spi@78b5000 { /* BLSP1 QUP3 */
+ compatible = "qcom,spi-qup-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "spi_physical", "spi_bam_physical";
+ reg = <0x78b5000 0x600>,
+ <0x7884000 0x1f000>;
+ interrupt-names = "spi_irq", "spi_bam_irq";
+ interrupts = <0 95 0>, <0 238 0>;
+ spi-max-frequency = <50000000>;
+ pinctrl-names = "spi_default", "spi_sleep";
+ pinctrl-0 = <&spi1_default &spi1_cs0_active>;
+ pinctrl-1 = <&spi1_sleep &spi1_cs0_sleep>;
+ clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
+ <&clock_gcc clk_gcc_blsp1_qup1_spi_apps_clk>;
+ clock-names = "iface_clk", "core_clk";
+ qcom,infinite-mode = <0>;
+ qcom,use-bam;
+ qcom,use-pinctrl;
+ qcom,ver-reg-exists;
+ qcom,bam-consumer-pipe-index = <4>;
+ qcom,bam-producer-pipe-index = <5>;
+ qcom,master-id = <86>;
+ status = "disabled";
+ };
+
+
+spi_3: spi@78b7000 { /* BLSP1 QUP3 */compatible = "qcom,spi-qup-v2";#address-cells = <1>;
diff --git a/arch/arm64/boot/dts/qcom/sdm450-qrd-sku4.dtsi b/arch/arm64/boot/dts/qcom/sdm450-qrd-sku4.dtsi
index 57b54a7..536e4da 100644
--- a/arch/arm64/boot/dts/qcom/sdm450-qrd-sku4.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm450-qrd-sku4.dtsi
@@ -247,6 +247,18 @@};*/+&spi_1{
+ status = "ok";
+ spi_ir@1 {
+ compatible = "qcom,spi-msm-codec-slave";
+ reg = <1>;
+ spi-max-frequency = <50000000>;
+ spi-cpol;
+ status = "ok";
+ };
+};
+
+/*WT-fangzhihua.TP.Function, 20198/07/14, add for noflash*/&spi_3 {/* Novatek device tree node */
五、如果一配置完相关的gpio，烧录boot.img之后系统进入900E模式，是由于在TZ限制了访问权限导致的，到相关的目录修改GPIO的访问权限从cp侧调整到ap侧
