全志 a10 linux,全志A10处理器参数介绍

news/2024/10/17 8:26:41/

全志A10是中国工信部软件与集成电路2011年8月研发的单核移动应用处理器。采用55nm工艺,芯片集成了四倍全高清视频解码技术、智能功耗管理系统、高清多屏显示处理及输出、高速高效系统体系架构、数模混合高速信号先进工艺的设计与集成、智能电能平衡等多项领先技术,A10主要应用于平板电脑、高清播放器、智能手机、网络机顶盒、智能电视一体机等。

A10芯片参数

CPU

ARM CortexTM-A8 32-Bit RISC

Processor ARMv7 Instruction set plus Thumb-2 Instruction Set

32KB Instruction Cache and 32KB Data Cache

256KB L2 Cache

NEONTM SIMD Coprocessor

Jazelle RCT Acceleration

Trustzone technology with secure transactions and digital right

managements(DRM)

GPU

3-dimensional (3D)

Industry standard API support :Open GL ES 2.0 / open VG

1.1

2-dimensional (2D)

support BLT / ROP2/3/4 support 90/180/270 degree Rotation

support Mirror / alpha (including plane and pixel alpha) / color

key

Support format convertion

VPU

Video Decoding (FULL HD)

Support VP8, AVS, H.264, H.263, VC-1,MPEG-1/2/4

standards

Up to 1920*1080@60fps

Video Encoding Support encoding in H.264 High Profile format

1080p@60fps

720p@100fps

Display Processing Ability

Four moveable and size-adjustable

layers

8 tap scale filter in horizontal and 4 tap in vertical direction

for scaling

Multi-format image input support Alpha blending / color key /

gamma support Hardware cursor / sprite

support Vertical keystone correction

support Output color correction (luminance / hue / saturation

etc)

support motion adaptive de-interlace support Video enhancement (lum peaking / DCTi / black and white

level extension)

support 3D format content input/output format convert/display

(including HDMI)

Display Output Ability

Support HDMI V1.3/V1.4

Flexible LCD interface (CPU / Sync RGB / LVDS) up to 1920*1080

resolution

CVBS / YPbPr up to 1920*1080 resolution

Image Input Ability

Dual camera sensor interface (CSI0 supports ISP

function)

Memory

16/32-bits SDRAM

controller support DDR2 SDRAM and DDR3 SDRAM up to 800Mbps

Memory Capacity up to 16 G-bits

8-bits NAND Flash Controller with 8 chip select and 2 r/b

signals

Support SLC/MLC/TLC/DDR NAND

ECC up to 64 bits

Peripheral

1

USB 2.0 Dual-Role Device(DRD) controller for general application,2

USB EHCI controller for host application

4 high-speed Memory controller supports SD version 3.0 and MMC

version 4.2

8 UARTs with 64 Bytes TX FIFO and 64 Bytes RX FIFO

One UART with full modem

function

Two UARTs with RTS/CTS

hardware flow control

Five UARTs with two

wires

4 SPI controller

1 dedicated SPI controller

for serial NOR Flash boot application

3 SPI for general

applications

4 SD/MMC controller

2 PS2 controller for connecting external PS2 mouse and PS2

keypad

3 Two-Wire Interface up to 400Kbps

Key Matrix (8x8) with internal debounce filter

IR controller supports MIR, FIR and IR remoter

2-channel 6-bits LRADC for line control

Internal 4-wire touch panel controller with pressure sensor and

2-point touch I2S/PCM controller for 8-channel output and 2-channel

input

AC97 controller compatible with AC97 version 2.3 standard

Internal 24-bits Audio Codec for 2 channel headphone, 2 channel

microphone, 2 channel FM input and Line

input

2 PWM controller

System

8

channel normal DMA and 8 channel dedicateed DMA

Internal (32K+64K) SRAM on chip

6 timer, 1 RTC timer and 1 watchdog

Security

Security System

Support DES, 3DES, AES encryption and decryption.

Support SHA-1, MD5 message digest Support hardware random generator 128-bits EFUSE chip ID

Package

TFBGA441package

0.8mm pitch


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