PIN

定义

DCD

数据载波检测

RXD

接受数据

TXD

发送数据

DTR

数据终端准备

GND

地线

DSR

数据准备就绪

RTS

请求发送

CTS

清除发送

RI

振铃提示

Pin nubmber

Pin Description

1

---->  #STROBE 数据选通

2

D0

3

D1

4

D2

5

D3

6

D4

7

D5

8

D6

9

D7

10

<----  #ACK    应答脉冲

11

                                    <----  BUSY    忙

12

<----  PE      打印纸尽

13

<----  SLCT    选择

14

---->  #AUTOFD 自动进纸

15

<----  #ERROR  错误

16

---->  #INIT   初始化

17

    ---->  #SELIN  打印机选择输入

18

GND

19

GND

20

GND

21

GND

22

GND

23

GND

24

GND

25

GND

Pin

I/O

定义

VCC12A_AUX

VCC12A

VCC12A_PLL

PWR

1.2V Analog Power Supply

VCCK

PWR

1.2V Digital Power Supply

VCC33A_PLL

VCC33A_AUX

VCC33A_LVDS

PWR

3.3V Analog Power Supply

VCC3IO

VCC33D_DLL

PWR

3.3V Digital Power Supply

GND12A

GND12A_PLL

GND33A_PLL

GND33A_AUX

GND33A_LVDS

GND33A_DLL

PWR

Analog Ground

GNDK

GND3IO

PWR

Digital Ground

Pin

I/O

定义

REFCLK_M

REFCLK_P

I

PCIe PHY differential PLL reference clock.

Cascade Mode: Pull down using 10K Resistor.

REXT

O

Bandgap External Resistor (Connect this pin to ground through an external resistor of 6.2KΩ, ±1%)

RXDN

RXDP

I

PCIe PHY differential positive serial data input.

Cascade Mode: Pull down using 10K Resistor.

TXDP

TXDN

O

PCIe PHY differential negative serial

data output.

Cascade Mode: Leave this pin as “No Connection”.

WAKE_n

O

This is an active low signal used to reactivate the PCI Express slot’s main power and reference clocks.

Cascade Mode: Leave this pin as “No Connection”.

CLK_SEL

O

Used to enable/disable clock of PCI Express card.

PCIe_RST_n

I

Active low asynchronous reset from PCIe RC

Pin

I/O

Description

SP1_TX

SP2_TX

O

Transmit data out to transceiver

or IrDA data out to IR LED

SP1_DTR_n

SP2_DTR_n

O

Data terminal ready (Active Low)

SP1_RTS_n

SP2_RTS_n

O

Request to send (Active Low)

SP1_RX

SP2_RX

I

Serial receives data in from transceiver or IrDA data in from IrDA detector.

SP1_RI_n

SP2_RI_n

I

Ring Indicator (Active Low)

SP1_DSR_n

SP2_DSR_n

I

Data Set Ready (Active Low)

SP1_DCD_n

SP2_DCD_n

I

Data Carrier Detect (Active Low)

SP1_CTS_n

SP2_CTS_n

I

Clear to send (Active Low)

Pin

I/O

Description

STROBE_n

O

Set active low by the host to transfer data into the input latch of the peripheral. Data are valid while STROBE_N is low.

AUTOLF_n

O

The interpretation of this signal varies from peripheral to peripheral.

Set low by host to put some printers into auto-line feed mode

INIT_n

O

Pulsed low by the host in conjunction with IEEE 1284 Active low to reset the interface and force a return to Compatibility Mode idle phase

SELECTIN_n

I/O

Set low by host to select peripheral

ACK_n

I

Pulsed low by the peripheral to acknowledge transfer of a data byte from the host

BUSY

I

Driven high by the peripheral to indicate that it is not ready to receive data

PAPEREND

I

Driven high by the peripheral to indicate that is has encountered an error in its paper path. The meaning of this signal varies from peripheral to peripheral.

Peripherals shall set FAULT_N low whenever PAPEREND is set high

SELECT

I

Set high to indicate that the peripheral is online

FAULT_n

I

Set low by the peripheral to indicate that an error has occurred. The meaning of this signal varies from peripheral to peripheral

PP_DIR

O

Set low to indicate a data transfer direction of peripheral to host and set high to indicate a data transfer direction of host to peripheral

DATA_[0:7]

I/O

Driven by the host in Compatibility Mode and the negotiation phase, not used in Nibble Mode, and bidirectional in all other modes

Pin

I/O

Description

CASC_REQ

I/O

To request the arbiter to grant access to CASC_AD bus

CASC_ACK

I/O

Asserted by slave, in response to CASC_VAL,  when it is ready to accept transfer

CASC_VAL

I/O

1:address/data/command on CASC_AD [7:0] is valid

0: CASC_AD is not valid

CASC_AD[0:7]

I/O

To transfer Address / Data and control words

CASC_GNT

I/O

Grant to access of CASC_AD bus

CASC_EN

I

1 : cascade mode enabled

0 : cascade mode disabled

CASC_PRIM

I

Chip is cascade secondary. Leave this pin as “No Connection”

SEC_DEV_MODE

O

For Non-Cascade applications, leave this pin as No Connect. When MCS9901CV-CC is used as Cascade Secondary Device, connect this pin to corresponding pin of the Cascade Primary Device. 

SEC_DEV_ID

I

Leave this pin as “No Connection”

CASC_CLK

O

Pull down using 1K resistor

Pin

I/O

Description

I2C_SCL

I/O

2-Wire EEPROM Clock

I2C_SDA

I/O

2-Wire EEPROM Data in/out.

Pin

I/O

Description

GPIO_[0:5]

I/O

General Purpose I/O signal

Pin

I/O

Description

XTAL_I

I

Crystal input for PLL, 24～42MHz

XTAL_IO

I/O

Feedback signal for the oscillator pad

Pin

I/O

Description

SCAN_EN

I

Scan enable signal

SCAN_MODE

I

This signal is used as clock input in cascade mode.

Cascade mode: Cascade Clock driven by ‘primary’ through ‘CASC_CLK’ should be interfaced to this pin.

Non-Cascade Mode: Pull Down using 1K resistor.

Pin number

I/O

Description

TCK

I

JTAG chain clock

TDI

I

JTAG chain input

TDO

O

JTAG chain output

TMS

I

JTAG chain Test mode select

TRST_n

I

JTAG Reset

(pull-up is recommended on JTAG Reset)

Pin Description

数目（个）

Power & Gnd

41

PCIe Interface Signals

10

Serial ATA Interface Signals

8X2=16

Parallel port Interface signals

18

Cascade Interface Signals

17

I2C Interface Signals

2

GPIO Interface Signals

6

Clock/Crystal Oscillator Interface Signals

2

Test Mode Signals

2

JTAG Interface Signals

5

NC

9