EDA实验设计-led灯管动态显示；VHDL；Quartus编程

embedded/2024/11/21 14:07:14/

EDA实验设计-led灯管动态显示；VHDL；Quartus编程

引脚配置
实现代码
RTL引脚展示
现象记录
效果展示

引脚配置

#------------------GLOBAL--------------------#
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFFset_location_assignment PIN_28  -to CLOCKset_location_assignment	PIN_50	-to	DIG[0]
set_location_assignment	PIN_53	-to	DIG[1]
set_location_assignment	PIN_54	-to	DIG[2]
set_location_assignment	PIN_55	-to	DIG[3]
set_location_assignment	PIN_176	-to	DIG[4]
set_location_assignment	PIN_47	-to	DIG[5]
set_location_assignment	PIN_48	-to	DIG[6]
set_location_assignment	PIN_49	-to	DIG[7]set_location_assignment	PIN_156	-to	SEG[0]
set_location_assignment	PIN_158	-to	SEG[1]
set_location_assignment	PIN_141	-to	SEG[2]
set_location_assignment	PIN_143	-to	SEG[3]
set_location_assignment	PIN_124	-to	SEG[4]
set_location_assignment	PIN_123	-to	SEG[5]
set_location_assignment	PIN_122	-to	SEG[6]
set_location_assignment	PIN_121	-to	SEG[7]
#------------------END-----------------------#

实现代码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE WORK.ZXQPALC.ALL;
ENTITY LED_8 IS generic( M: integer  :=48000 ; N: integer  :=8  ) ; PORT(    CLOCK :	IN STD_LOGIC;SEG : OUT STD_LOGIC_VECTOR(7 downto 0);DIG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END LED_8;ARCHITECTURE BHV OF LED_8 ISBEGINPROCESS(CLOCK)VARIABLE CQI_1:integer range 0 to M;VARIABLE CQI_2:integer range 0 to N;BEGINIF CLOCK'EVENT AND CLOCK='1' THENIF CQI_1<(M-1) THEN  CQI_1:=CQI_1+1; ELSE CQI_1:=0;IF CQI_2<(N-1) THEN CQI_2:=CQI_2+1;    ELSE CQI_2:=0;END IF ;END IF ;	CASE CQI_2 ISWHEN 0      =>  SEG<=B"1100_0000"; DIG<=B"0111_1111";WHEN 1      =>  SEG<=B"1111_1001"; DIG<=B"1011_1111";WHEN 2      =>  SEG<=B"1010_0100"; DIG<=B"1101_1111";WHEN 3      =>  SEG<=B"1011_0000"; DIG<=B"1110_1111";WHEN 4      =>  SEG<=B"1001_1001"; DIG<=B"1111_0111";WHEN 5      =>  SEG<=B"1001_0010"; DIG<=B"1111_1011";WHEN 6      =>  SEG<=B"1000_0010"; DIG<=B"1111_1101";WHEN 7      =>  SEG<=B"1111_1000"; DIG<=B"1111_1110";WHEN OTHERS   =>  SEG<=B"1111_1111"; DIG<=B"1111_1111";END CASE;END IF;END PROCESS ;
END BHV;