【Verilog】big_small

通用大小计数器

`timescale 1ns / 1ps
//
// Company: 
// Engineer:    wengf
// Create Date: 
// Design Name: 
// Module Name: big_small_cnt
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// Dependencies: 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 通用的大小计数器，输入想要开始的条件，直到条件终止
//
module big_small_cnt(
clk       ,
rst       ,
clk_p     ,
start     ,//BIG_LENGTH,// 添加big_cnts  ,
small_cnts);
//    
parameter BIG_LENGTH=16'd8;
parameter SMALL_LENGTH=8'd11;
//
input clk,rst,clk_p,start;
//input [15:0] BIG_LENGTH;//添加output [15:0] big_cnts;
output [7:0] small_cnts;
//
reg [7:0] small_cnts;
always @ (posedge clk or posedge rst)//小计数器
beginif(rst)beginsmall_cnts<=8'hff;endelse if(clk_p)beginif(start)//起始位置beginsmall_cnts<=8'd0;	endelse if((small_cnts==SMALL_LENGTH-1)&&(big_cnts<BIG_LENGTH-1))//所需长度减1,在这里面进行循环，当big_cnt大于该长度后，自动停止beginsmall_cnts<=8'd0;		endelse if(big_cnts<=BIG_LENGTH-1)//所需长度减1,在这里面进行循环，当big_cnt大于该长度后，结束循环，保持循环达不到的最大值beginsmall_cnts<=small_cnts +1'b1;			endelsebeginsmall_cnts<=small_cnts;		endendelsebeginsmall_cnts<=small_cnts;			end
end
//
reg [15:0] big_cnts;
always @ (posedge clk or posedge rst)
beginif(rst)beginbig_cnts<=16'hffff;endelse if((start)&&(clk_p))//起始位置 beginbig_cnts<=16'd0;	endelse if((small_cnts==SMALL_LENGTH-1)&&(clk_p))所需长度减1，最大值受最小值控制，按照最小值走几个周期即可。beginbig_cnts<=big_cnts + 1'b1;		endelsebeginbig_cnts<=big_cnts;			end
end
//endmodule

通用大小计数器，去除 clk_p

`timescale 1ns / 1ps
//
// Company: 
// Engineer:    wengf
// Create Date: 
// Design Name: 
// Module Name: big_small_cnt
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// Dependencies: 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 通用的大小计数器，输入想要开始的条件，直到条件终止
//
module big_small_cnt(clk             ,rst             ,start           ,forward_cnts    ,backward_cnts   , big_cnts        ,small_cnts      ,small_pulse_start,small_pulse_end,pulse_end
);parameter BIG_LENGTH=16'd8;
parameter SMALL_LENGTH=8'd8;
parameter COUNT = BIG_LENGTH * SMALL_LENGTH;input clk,rst,start;
output [15:0] forward_cnts,backward_cnts;
output [15:0] big_cnts;
output [7 :0] small_cnts;
output small_pulse_start;
output small_pulse_end;
output pulse_end;reg [15:0] forward_cnts,backward_cnts;
reg [15:0] big_cnts;
reg [7:0] small_cnts;
reg small_pulse_start,small_pulse_end,pulse_end;always @ (posedge clk or posedge rst)//小计数器
beginif(rst)beginforward_cnts<=16'hffff;endelse if(start)//起始位置beginforward_cnts<=16'd0;	endelse if(big_cnts<=BIG_LENGTH-1)//所需长度减1,在这里面进行循环，当big_cnt大于该长度后，结束循环，保持循环达不到的最大值beginforward_cnts<=forward_cnts +1'b1;			endelsebeginforward_cnts<=forward_cnts;		end
endalways @ (posedge clk or posedge rst)//小计数器
beginif(rst)beginbackward_cnts <= 16'hffff;endelse if(start)//起始位置beginbackward_cnts <= COUNT-1'b1;	endelse if(big_cnts<=BIG_LENGTH-1)//所需长度减1,在这里面进行循环，当big_cnt大于该长度后，结束循环，保持循环达不到的最大值beginbackward_cnts<=backward_cnts-1'b1;			endelsebeginbackward_cnts<=backward_cnts;		end
endalways @ (posedge clk or posedge rst)//小计数器
beginif(rst)beginsmall_cnts<=8'hff;endelse if(start)//起始位置beginsmall_cnts<=8'd0;	endelse if((small_cnts==SMALL_LENGTH-1)&&(big_cnts<BIG_LENGTH-1))//所需长度减1,在这里面进行循环，当big_cnt大于该长度后，自动停止beginsmall_cnts<=8'd0;		endelse if(big_cnts<=BIG_LENGTH-1)//所需长度减1,在这里面进行循环，当big_cnt大于该长度后，结束循环，保持循环达不到的最大值beginsmall_cnts<=small_cnts +1'b1;			endelsebeginsmall_cnts<=small_cnts;		end
endalways @ (posedge clk or posedge rst)//小计数器
beginif(rst)beginsmall_pulse_start<=1'b0;endelse if(start)//起始位置beginsmall_pulse_start<=1'b1;endelse if((small_cnts==SMALL_LENGTH-1)&&(big_cnts<BIG_LENGTH-1))//所需长度减1,在这里面进行循环，当big_cnt大于该长度后，自动停止beginsmall_pulse_start<=1'b1;	endelsebeginsmall_pulse_start<=1'b0;	end
endalways @ (posedge clk or posedge rst)//小计数器
beginif(rst)beginsmall_pulse_end <= 1'b0;endelse if(start)//起始位置beginsmall_pulse_end <= 1'b0;endelse if(small_cnts==SMALL_LENGTH-2)//所需长度减1,在这里面进行循环，当big_cnt大于该长度后，自动停止beginsmall_pulse_end <=8'd1;		endelsebeginsmall_pulse_end <= 1'b0;end
endalways @ (posedge clk or posedge rst)
beginif(rst)beginbig_cnts<=16'hffff;endelse if(start)//起始位置 beginbig_cnts<=16'd0;	endelse if(small_cnts==SMALL_LENGTH-1) beginbig_cnts<=big_cnts + 1'b1;		endelsebeginbig_cnts<=big_cnts;			end
end// pulse_end
always @ (posedge clk or posedge rst)
beginif(rst)beginpulse_end<=1'b0;endelse if(start)//起始位置 beginpulse_end <= 1'b0;endelse if((small_cnts==SMALL_LENGTH-1) && (big_cnts==BIG_LENGTH-1)) beginpulse_end <= 1'b1;endelsebeginpulse_end <= 1'b0;end
endendmodule

在这里插入图片描述

wire [15:0] forward_cnts,backward_cnts;
wire [15:0] big_cnts;
wire [7:0] small_cnts;
wire small_pulse_start,small_pulse_end;
wire pulse_end;big_small_cnt
# ( .BIG_LENGTH(16'd8), .SMALL_LENGTH(16'd3))
big_small_cnt(.clk                (clk),.rst                (rst),.start              (cnts == 8'd10),.forward_cnts       (forward_cnts),.backward_cnts      (backward_cnts),.big_cnts           (big_cnts),.small_cnts         (small_cnts),.small_pulse_start  (small_pulse_start),.small_pulse_end    (small_pulse_end),.pulse_end          (pulse_end)
);